1. Field of the Invention
The present invention generally relates to an electrostatic discharge (ESD) protecction circuit for integrated circuits. More particularly, the present invention relates to a method of fabricating a low-voltage zener-triggered silicon-controlled rectifier.
2. Description of the Related Art
Electrostatic discharge, ESD hereafter, is a common phenomenon that occurs during handling of semiconductor IC devices. An electrostatic charge may accumulate for various reasons and cause potentially destructive effects on an IC device. Damage typically can occur during a testing phase of its fabrication, during assembly of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can hamper some of its designed functions, or sometimes all of them. ESD protection for semiconductor ICs is, therefore, a reliability problem.
ESD stress models are based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standard models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been developed. The human-body model is set forth in U. S. Military Standard MIL-STD-883, Method 3015.6. This Military Standard models the electrostatic stress produced on an IC device when a human carrying an electrostatic charge touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying an electrostatic charge contacts the lead pins of the IC device. The charged device model describes the ESD current pulse generated when an IC device already carrying an electrostatic charge is grounded while being handled.
However, in light of the trend toward submicron scale IC fabrication, CMOS IC vulnerability to the ESD stress has been greatly reduced due to advanced processes, such as lightly-doped drains (LDD) structure and clad silicide diffusions. Lateral silicon controlled rectifiers (LSCR) have been utilized as the main components of ESD protection circuits for facilitating protection, while allowing the submicron semiconductor devices to function acceptably. An example, R. N. Rountree et al., "A PROCESS-TOLERANT INPUT PROTECTION CIRCUIT FOR ADVANCED CMOS PROCESSES," has been proposed in EOS/ESD Symp. Proc., EOS-10, pp.201-205, 1988.
However, there is one inherent constraining design factor for the lateral SCR's used in ESD protection circuits for sub-micron semiconductor devices. The trigger voltage for lateral SCR's in sub-micron CMOS devices is in the range of 30 to 50 Volts. The typical thickness of gate oxide layers in CMOS fabrication processes employing a resolution of 0.6-0.8 microns is about 150-200 angstroms. Considering a dielectric breakdown strength of 10 MV/cm for typical SiO.sub.2 material, the gate oxide layers in these sub-micron CMOS devices would be destroyed by a voltage of about 15-20 volts. Furthermore, as an example, for 0.5 m feature size CMOS technology with a gate oxide thickness of 105 angstroms, measurable Flower-Nordheim tunneling through the gate oxide starts at around 7 V and the breakdown occurs at 14.5 V. Therefore, lateral SCR's with a trigger voltage in the range of 30-50 volts must be fitted with other protection components so that they can provide protection for gate oxide layers in sub-micron CMOS IC devices.
Efforts have been made to lower the trigger voltage of lateral SCR's in the ESD protection circuits for the sub-micron CMOS device. The trigger voltage should be reduced to below the dielectric breakdown voltage of the gate oxide layers of the CMOS device, so that the ESD protection circuits can provide protection for the CMOS device before being damaged themselves. Several ways to lower the trigger voltage of lateral SCR have been proposed.
In one approach, A. Chatterjee and T. Polgreen proposed a low-voltage trigger SCR (LVTSCR) configuration in "A LOW-VOLTAGE TRIGGERING SCR FOR ON-CHIP ESD PROTECTION AT OUTPUT AND INPUT PADS, " IEEE Electron Device Letters, 12(1), 1991, pp.21-22. In their disclosure, Chatterjee and Polgreen employed a short-channel NMOS transistor coupled to an SCR to form the low-voltage trigger SCR having a trigger voltage that is about equal to the breakdown voltage (BV.sub.dss) of the short-channel NMOS transistor.
Moreover, U. Sharma et al., "AN ESD PROTECTION SCHEME FOR DEEP SUB-MICRON VLSI CIRCUITS," 1995 Symposium on VLSI Technology Digest of Technical Papers, pp.85-86, present another low-voltage SCR configuration for an ESD protection circuit. Referring to FIG. 1, reference numerals 1 and 2 designate an Input/Output pad and an internal circuit to be protected. The internal circuit 2 is tied to the Input/Output pad 1 via a conducting line 3. An SCR device serves as the main component in a protection circuit. In the drawing, the SCR device consists essentially of a pnp bipolar junction transistor T.sub.1 and an npn bipolar junction transistor T.sub.2. The collector of the pnp transistor T.sub.1 is connected together with the base of the npn transistor T.sub.2, forming a cathode gate identified by the node 7. The cathode gate 7 is coupled to the emitter of the npn transistor T.sub.2, via a spreading resistor R.sub.p, constituting a cathode 5 which is connected to a V.sub.SS terminal of the CMOS IC device. The base of the pnp transistor T.sub.1 is connected together with the collector of npn transistor T.sub.2 to form an anode gate identified by the node 6. The anode gate 6 is coupled to the emitter of the pnp transistor T.sub.1, via a spreading resistor R.sub.n, constituting an anode 4 which is connected to the conducting line 3.
As shown in FIG. 1, a zener diode Z.sub.1 is incorporated to lower the trigger voltage of the lateral SCR device constituted by the bipolar transistors, T.sub.1 and T.sub.2. The zener diode Z.sub.1 is provided with a cathode terminal and an anode terminal connected to the anode gate 6 and the cathode gate 7 of the lateral SCR device, respectively. When an ESD event occurs, the zener diode Z.sub.1 breaks down and triggers the lateral SCR device to latchup which starts in the high conduction state. Once the latchup happens, the ESD current is mainly discharged through the lateral SCR device. Accordingly, the ESD stress on the Input/Output pad 1 is clamped by the holding voltage of the turned-on lateral SCR device to about 1-2 Volts so as to protect the internal circuit 2 which is connected to the Pad 1. Usually, the zener-triggered SCR device has a trigger voltage that is about equal to the breakdown voltage of the zener diode Z.sub.1, ranging from about 5 Volts to about 7 Volts.